How to overcome the challenges of FPGA board design
If you have limited or no experience with board design using FPGAs, the prospect of using FPGAs in new projects is worrisome—especially if the FPGA is a large block with 1000 pins. Keep reading this article will help you with your FPGA selection and design process and help you avoid many of the challenges.
Select a supplier
The first problem you face is of course the choice of suppliers and devices. Often vendor decisions tend to be the ones you've been most exposed to before—if you're an FPGA beginner, of course. Perhaps this decision has already been made by engineers who design internal logic (perhaps you) based on familiar vendors or third-party IP and their costs.
The vendor's software tools also affect the above decisions. Download and use these software tools to bring your design to the simulation phase without the need for hardware. This is also a way to judge how large an FPGA is needed, provided that your internal logic design is basically done.
To know how deep the FPGA water is, you need to visit the websites of various suppliers. If you want to get the most out of the massive (and not always clear) information provided by these sites, you must make sure you have a free day. Altera and Xilinx are two companies that are far ahead in terms of market share and cutting-edge technology. Their devices use internal configuration RAM, so external ROMs that store configuration data are required to "boot" the device (both companies also have small non-volatile CPLDs). Other vendors worth considering are Microsemi/Actel, Lattice and Cypress. Their device capabilities include very low static power, ROM-based configuration for "on-the-fly" boot, and analog peripherals.
Ok, so far the supplier problem has been solved. The next step is to choose the series and size of the FPGA. Vendors break down their products into multiple series, often distinguished by vague concepts such as low-end, mid-range, and high-end performance (and scale). How large is the on-chip RAM? How many DSP/multiplication blocks, or gigabit transceivers? You may need to read through the data sheet to find parameters such as maximum clock frequency and I/O delay to help you choose the right series. It's important to reiterate that having HDL code is a great help because design software lets you know which device is right and whether it meets your performance requirements.
Your application can also benefit from updating the device without changing the PCB. Some FPGA families include a wide range of pin-compatible devices that allow you to switch to larger (or cheaper and smaller) devices when needed. Just be sure to design for the minimum number of pin outputs.
Don't forget to consider other details such as how to separate I/O groups, PLL requirements, and DDR interface requirements for different supply voltages and I/O standards.
We need more power!
It is often difficult to calculate the maximum current required for a board. But the FPGA power supply design is quite tricky. The current required by the FPGA is highly dependent on the logic design and clock frequency. The same device may only require 0.5W in one design and up to 5W in another design.
Development tools (or a stand-alone program or spreadsheet) should be able to provide power estimates for a given design, but they need to get a lot of additional information from you, some of which may be justified speculation. If you have an FPGA development board, you should have a way to measure the supply current in each case. Some development boards even embed galvanometer displays! Just make sure to add enough headroom to accommodate design changes and special process/temperature requirements.
Here's how the "difficulties" might appear:
● Do thermal analysis and add heat sinks if necessary.
● Does the FPGA require power up in sequence? (Your design is prone to 5 or 6 power supplies)
● At least one “quiet” power supply may be required, typically for on-chip PLLs. You can use LDOs with some passive filter components. Gigabit transceiver power supplies can also benefit from low noise.
● Make sure you understand what the FPGA is doing during power up and initialization. Many devices require a large amount of current to be drawn at this time.
About pins and others
Next, you can seriously consider the pin assignment. Also, if your logic design has reached a stage where it can be compiled, let the design software help, or at least verify that the pins you have assigned are working before you do the board. You have of course dealt with obvious resources, such as dividing the I/O group according to the supply voltage, ensuring that the "special" pin settings such as LVDS, SSTL or internal 50Ω terminals are compatible with the group and supply voltage they are in.
But there are deeper subtleties in many devices: "Don't place a differential pair in two IC-bonded pads of a single-ended signal," or "an input similar to a reference voltage must have at least 3 pads from the clock signal. There are complex rules between lines in the word "far". These rules are easy to make people crazy. If you are unbearable, let the design software point you to the violation. If you don't do this, then these problems will definitely make you exhausted.
Ground bounce or concurrent switching noise (SSN) is another consideration. Because FPGAs are used in too many ways, vendors often design power distribution schemes for the best scenarios. If your design wants to take full advantage of I/O capabilities, such as using a large number of fast simultaneous switching outputs, you may need to "reduce" the number of pins that can actually be used. It is usually a good idea to minimize the drive and slew rate settings. Design software may also help with SSN analysis. I think one trick to reduce SSN is to connect unused pins to ground and then set them to output in the design file, driving '0'. These pins will be used as pseudo ground pins, although the quality is not really good.
Now is the time to deliver the products that have condensed your efforts to the PCB layout design. I don't want to go into the PCB design here (you can refer to some of the articles given below), but I will point out some things to consider for FPGA design.
Stacking is important for any complex board, and FPGAs are often found in the most complex boards. As the 500-pin chip is considered "medium-scale" and shrinking pin pitch, you may want to pay close attention to the trace escape pattern, vias in the pads, decoupling capacitors in the pin area, and power and ground. flat. Be creative. The power plane can be split if necessary (of course avoid high-speed routing). If you are careful enough, some power connections (usually local power supplies, such as PLL power supplies) can be placed on the signal layer. Place some key planes and signals at the layer closest to the FPGA. Keep an eye out for some special layout suggestions, such as some suggestions for DRAM.