EDA Mentor International Calibre platform has supported the latest TSMC 12FFC process design

As the 7nm process of the first-line wafer foundry is about to enter trial production and mass production, Electronic Design Automation (EDA) is also rapidly catching up, providing various solutions for the 7nm and 12nm processes. EDA industry leader Mentor Graphics announced that the company's Calibre design tool platform includes design specification inspection (DRC), multiple exposure (Multi-Patterning), layout winding (P&R) tools, etc. Meter FFC and 7 nm V1.0 process certification. Calibre now supports the latest TSMC 12FFC process design to assist customers in their designs. In addition, the AFS circuit verification platform, including the AFS Mega, has mature readiness to support 12FFC technology and the TSMC Modeling Interface (TMI).

For TSMC's 7nm process, the complete Calibre implementation kit has been updated to version V1.0 for customer production design delivery manufacturing. After several revisions, TSMC and Mentor continued to work together to improve the performance of Calibre DRC. The current V1.0 version has significantly improved execution speed compared to the initial version.

EDA明导国际Calibre平台已支持最新的TSMC 12FFC制程设计

Reliability is a key factor in the success of many electronic products today. TSMC and Mentor International have expanded their partnership to the 7nm process to provide complete electrostatic discharge (ESD) and latch-up verification, all of which have an impact on reliable performance and product life. This partnership also led to the development of multi-CPU computing functions in the Calibre PERC tool that can be used to perform fully designed point-to-point (P2P) impedance and current density (CD) checks.

The Engineering Change Order (ECO) usually occurs at a later stage of the design process and affects the time course of delivery. In order to accelerate the ability of both customers to achieve design convergence, TSMC cooperated with Mentor International to expand the Calibre YieldEnhancer ECO filling process from 20 nm to the latest 7 nm technology. The ECO fill process allows customers to quickly manage design changes at the final stage and ensure that changes are still in line with TSMC's manufacturing needs.

The AFS platform, including the AFS Mega circuit simulator, has been certified by TSMC's 7nm V1.0 process. The analog, mixed-signal and RF design teams of the world's leading semiconductor industry will benefit from the AFS platform to effectively validate chips designed using TSMC's latest technology.

Mentor's Nitro-SoC P&R platform has been further enhanced to meet all of TSMC's 7nm design implementation and certification requirements. Mentor also demonstrated the maturity of its 7nm technology, and successfully built the ARM processor through the Nitro-SoC P&R platform, which is now available to customers.