At CES, Intel demonstrated the first 10 nanometer Ice Lake processor
For a long time, several generations of Core processor architectures have been slightly improved, and the performance improvement has been small, and they have been given the nickname "Toothpaste Factory" by consumers. On the other hand, rival AMD is applauded by the desktop Ryzen processor. Although the EPYC processor in the server field has not caused serious threats to Xeon for a while, if Intel does not make any big mistakes, it is afraid to worry about further failure.
Finally, the sleeping tiger is going to be angry.
At this year's CES, Intel demonstrated the first 10 nanometer Ice Lake processor, which integrates Intel's new "Sunny Cove" microarchitecture, AI accelerated instruction set and 11th generation core graphics card with high integration. Graphics performance. Later in 2019, Sunny Cove will be the infrastructure for next-generation PC and server processors.
In fact, as early as in the past few years, there have been rumors that Intel has realized that the Core architecture system has begun to be difficult to cope with future development needs, and will launch a new architecture system around 2020, which is exactly the same as today. To a certain extent, it also shows that Intel's planning for the development route is relatively comprehensive and long-term.
According to Intel's published information, Ice Lake will not only use the 10nm process, but also adopt the new micro-architecture "Sunny Cove", which aims to improve performance and energy efficiency, support general-purpose computing and dedicated tasks such as AI artificial intelligence, encryption and networking.
In Core processors, Sunny Cove will provide new integration features to accelerate AI workloads, more security features, and significantly improve parallelism to enhance the gaming and media application experience.
Although the technical details of the Sunny Cove architecture have not yet been fully announced, many of the technical points revealed by Intel are enough to make people excited and expect:
A new algorithm that reduces latency is used.
An enhanced microarchitecture that performs more operations in parallel.
Increase the size of critical buffers and caches to optimize data-centric workloads.
Architecture extensions for specific use cases and algorithms. Added new instruction sets for cryptographic performance, such as vector AES and SHA-NI (7-ZIP compression decompression performance can be increased by 75%).
At the same time, as the type of computing in the data center is growing as the Cambrian explosion, Intel has been building a portfolio of different computing types, including Intel's traditional CPU, Arria and Stratix FPGAs, and its Crest neural network processing. And so on.
Listing is just around the corner
The 10nm Ice Lake processor and its PC-based products will be available in the holiday season at the end of 2019, and at the previous CES 2019 show, Intel also showed the real version of the mobile Ice Lake processor, and related notebooks. device.
Obviously, Ice Lake will follow the usual practice, starting with the mobile platform and then going to the desktop platform.
The release of 10nm Ice Lake will completely reverse Intel's embarrassing situation in the past two years, from technology to products, from market to strategy, all entering a new era. It can be said that after crossing this hurdle, Intel will re-enter a road.
According to Intel, the yield level of the 10nm process is satisfactory and will continue to improve, and the subsequent 7nm process will be smoother based on a series of advanced technologies harvested during the 10nm process development process.
At the same time, Intel reversed its acting style, looked forward to various future visions and beautiful blueprints, refocused on technology and products, and laid a more solid foundation. On the other hand, it proposed process technology, architecture, storage, and ultra-fine mutual The six strategic pillars of Lian, security and software guide the future development.
At CES, Intel demonstrated Lakefield, which uses a "Foveros" 3D package technology to mix CPU architecture and package architecture. It uses a 22FFL IO chip as the active carrier and a TSV (through-silicon via) to connect a 10nm chip. 1 Sunny Cove kernel and 4 Atom kernels (probably Tremont). The microchip is 12*12 in size and has a standby power of only 2mW.
As for the 10nm process, due to the complexity of transistor fabrication, comparisons with generations alone are no longer accurate. If the process level is measured by the transistor density commonly used in the industry, the transistor density of the Intel 10nm process is higher than that of TSMC's 7nm DUV process.