What kind of tools can guarantee the realization of cash
In terms of embedded systems and SOC, applications such as automotive, large-scale computing, IoT, and 5G communications have made the design of multi-core heterogeneous, multi-processing architectures mainstream. In the areas of driverless, AI and ML, multi-core heterogeneous chips are becoming more and more common, and in applications such as data centers, there are thousands of processors - as the function is iterated, this number will reach Millions of megabytes - running at the same time, the impact of interactions between these different processors on system-level behavior requires effective tracking and debugging.
In addition, the rise of new processor architectures such as rsIC-V has added an unprecedented option to SOC design. The increase in chip system complexity has led to an increase in chip design investment—a 7nm chip from design to tape It takes $200 million – so the tools that ensure they are properly designed and run to be realized are even more important.
Problems to be solved by large-scale system design
The complex interactions between multiple hardware modules, firmware and software in the SoC have made real-time full lifecycle monitoring an indispensable tool for SoC designers. Changes in design methods are also making monitoring of the entire system more necessary than ever. Flexible software development and special programming practices inherently require high detail visibility of the actual system. Similarly, the hardware and software build process requires engineers to clearly understand the behavior of their systems as they run.
"Chip designers always want to be able to perform system-on-chip development and debugging faster. System design requires enhanced connectivity, hardware-based security, functional security, field performance and power optimization," said UltraSoC CEO Officer Rupert Baines said. "Unlike the products offered by design tool companies such as Synopsys, UltraSoC products are IP-based in the user's chip. For the user, analysis and debugging is not only the development period, but also extends to the entire product life cycle." UltraSoC is a company that provides internal analysis, tracking and monitoring of IP for SoC designs. These IPs add scalable analytics and communication architectures to SoCs, including algorithms and tools for development, analysis and data visualization, as well as information security. analytical skills.
Figure: UltraSoC provides debugging and monitoring tools for SOC, supporting ARm, MIPS, RISC-V and other cpu architectures.
Development environment needs to be simplified
UltraSoC launched an integrated development environment tool, the UltraDevelop 2 IDE, in October last year. The tool integrates debugging, operational control, and performance tuning to provide an integrated view of hardware, firmware, and software operations, as well as advanced anomaly detection, visualization, and data science.
Figure: UltraDevelop 2 IDE provides an integrated view interface for hardware, firmware and software operation
Based on PercePIo's Tracealyzer feature, UltraDevelop 2 provides engineers with integrated visibility into hardware operations and advanced software execution. The integration of Imperas' multiprocessor debugger enables UltraDevelop 2 to support multi-core, multi-threaded platforms, including core combinations using different processor architectures, to support the development of complex heterogeneous systems - as mentioned above, these systems are becoming More and more common. "The purpose of creating UltraDevelop 2 is to give SoC designers the best combination of functionality and flexibility when choosing a development platform, and the ability to run real-time control over more than 20 CPU architectures." Baines said, "developers can Obtain and deploy third-party tools from existing UltraSoC partners and support the underlying UltraSoC hardware capabilities, or they can choose the pre-integrated configuration provided by UltraSoC."
Figure: The data processing capacity of the AI processor reaches 3Gbit/S. To analyze the delay and bandwidth, UltraDevelop 2 filters out invalid data through its own database comparison to improve the analysis efficiency.
UltraDevelop 2's system-wide approach to development means that developers can view and analyze the interaction between software and hardware at any level of abstraction. It is reported that the "wide-ranging debugging capability" highlighted by Microsemi's recently launched PolarFire SoC architecture is beneficial to this, which belongs to its RISC-V Mi-V ecosystem.
Special needs of RISC-V
As a fast-growing open source processor, RISC-V users are growing rapidly. It is reported that half of the current UltraSoC customers are from RISC-V, including Andes, Esperanto, Lauterbach, MICROCHIP and SiFive. "Esperanto's high-performance computing system places one thousand RISC-V processors and AI/ML accelerators on the same chip, and Western Digital promises to convert 1 billion cores in its storage processor to RISC-V architecture ( SweRV Core processor)," Baines said.
Unlike other processors such as ARM, which have built-in ETM (Embedded Trace Macrocell), RISC-V does not have ETM, so the company introduced the industry's first and only one for RISC-V in early 2018. The commercial tracking encoder IP is designed to encode instruction execution and data memory access and output a highly compressed tracking format that external software can then acquire and use to reconstruct the program execution flow. Other common features include data and instruction tracking, a range of counters and timers, and a quick analysis and rendering tool.
Hardware protection is more secure
From a security perspective, the analysis tool is preferably independent of the primary system and is non-intrusive. “Hardware protection analysis is faster and won't be discovered by malware,” Baines said. “At the same time, the results are also visible in real time and can be run by software. UltraDevelop 2 integrates hardware support such as anomaly detection and protection against malicious intrusions. Security and security features."
This hardware protection feature is based on UltraSoC's Bare Metal Security (BMS) technology, which provides a hardware-based level of security that is "lower than the operating system". For attackers, BMS is extremely difficult to detect. Or destroyed.
In addition to the increasing use of advanced hardware and software to interact with the physical world, the security requirements of the system are increasing. The proliferation of industry standards also requires high-level monitoring of the internal behavior of the SOC, not only during development, but also during development. Ability to perform analysis and debugging after deployment. Take the automotive network security standard SAE J3061, which requires monitoring and control of security functions throughout the product lifecycle, from development to field use, including attempts to monitor accidents and intrusion into the system and report such incidents. In addition, similar situations such as the freeze of the screen freezing misleading system also need to be able to make an early warning or assist the processing system to make decisions. This requires analysis tools to detect systemic and random errors in deployed products, enable new levels of security and security, and support on-site system health monitoring and advanced forensics.
"The UltraDevelop 2 infrastructure also includes features optimized for improving vehicle safety and security," Baines said. "Includes lockstep monitors for checking consistency between redundant modules." The device has a lockstep function, but in a multiprocessing architecture system, the third-party lockstep function is more objective.
It is reported that UltraSoC reached a cooperation plan in November last year with ResilTech, a company specializing in the design and verification of high-integrity critical system technology, to further improve the functional safety compliance of automotive systems against the ISO26262 standard.
Figure: Lockstep function monitoring prevents the processor from experiencing asynchronous frequency failures
The importance of accurate cycle tracking
In real-time and performance-critical applications, cycle-accurate tracking is becoming more and more important, and engineers need to optimize the operation of their hardware and software code to a single clock cycle level, ie by CPU, gpu, DsP Or the minimum time unit recognized by the accelerator.
UltraSoC recently added cycle-accurate tracking to its UltraDevelop 2 IDE, the RISC-V Trace Encoder tracking encoder, which supports both 32-bit and 64-bit RISC-V designs. The technology will initially be available as part of UltraSoC's RISC-V processor tracking solution.
Baines emphasizes that current processor tracking solutions only track program flows such as jumps, branches, interrupts, and so on. But you can't directly see what the CPU does at a particular moment, and accurate cycle tracking solves this problem.