Simplified design of capacitive digital isolators
At present, safety regulations regarding the use and design of electronic devices are endless, making galvanic is almost a necessity in all data acquisition and transmission systems. One way to avoid high voltage damage to the sensor and actuator components in the electric field of the low voltage circuit of the control system is to use a digital isolator.
The purpose of this article is to show you how to simplify the design of the isolation system. In addition to describing the basic functions of the capacitive digital isolator, the article details how to install the isolator in the signal path, and provides some valuable references for successfully designing the circuit board. opinion.
Basic functions of capacitive digital isolators
Figure 1 shows a simplified block diagram of a capacitive digital isolator consisting of a high speed signal path and a low speed signal path. The high speed path (blue portion) transmits signals from 100 kbps to 150 Mbps, while the low speed path (orange portion) transmits signals below 100 kbps to dc.
Figure 1 Simplified structure of a capacitive digital isolator
The high speed signal processed in the path shown in the blue portion is divided into a plurality of fast transient bursts by a capacitive isolation barrier. Subsequent flip-flops (FF) convert these transient bursts into pulses that are both waveform and phase consistent with the input signal. The internal watchdog (WD) checks the periodicity of the edge of the high speed signal. In the case of a low frequency input signal, the duration between successive signal edges exceeds the watchdog window. This forces the watchdog to change the output switch position from the high speed path (position 1) to the low speed path (position 2).
The low speed path has several more functional components than the high speed path. Because the low frequency input signal requires an isolation barrier to prohibit the use of large capacitance, the input signal is used to pulse width modulate (PWM) the carrier frequency of the internal oscillator (OSC). This constitutes a very high frequency that can pass through the capacitive barrier. Since the input is modulated, the high frequency carrier must be removed using a low pass filter (LPF) before the actual data is transmitted to the output.
Mounting position in the signal chain
Digital isolators are divided into single-channel, dual-channel, three-channel and four-channel devices that can operate in both unidirectional and bidirectional directions. Their common characteristics are as follows:
- does not meet any specific interface standard;
- Using 3V/5V logic switching technology
- Designed for electrically isolated digital, single-ended (SE) data lines
Although the last point seems to be a design limitation, Figure 2 shows how to isolate multiple interfaces, including low-voltage SPI, high-voltage RS232, differential USB, and differential CAN/RS485.
Figure 2 Digital isolators must be installed in the single-ended portion of the isolated interface
All interfaces have one thing in common, that is, the digital isolator must be installed in the single-ended 3V/5V portion of the isolated interface.
Since digital isolators have a rise and fall time of 1 to 2 ns, they tend to be subject to signal reflections in the case of long signal traces, and their characteristic impedance does not match the source impedance of the isolator output. Therefore, we recommend installing an isolator near its respective data sink and data source (eg controller, driver, receiver, transceiver, etc.). If this is not possible in the design, then a controlled impedance transmission line must be used.
PCB Design Guide
In the case of digital boards, standard FR-4 epoxy glass is used as the PCB material because it is not only UL94-V0 compliant, but also has less high frequency dielectric loss and more. Low hygroscopicity, greater strength/hardness and higher flame retardant properties.
To achieve low electromagnetic interference (EMI) PCB design, a minimum of four layers of design examples are recommended (see Figure 3), from top to bottom: high-speed signal layer, ground plane, power plane, and low-frequency signal layer.
Figure 3 Recommended four-layer laminate
Configuring high-speed traces on the top floor provides a clear connection to the isolator and its corresponding drive. High-speed traces should be short and avoid using vias to ensure low-speed trace inductance.
A balanced board ground plane is placed next to the high speed signal layer to ensure a strong electrical coupling between the ground plane and the signal trace. This establishes the controlled impedance of the transmission line interconnect and also greatly reduces EMI. Ultimately, balancing the ground plane of the board provides a very good low inductance path for reflow.
Place the power plane under the ground plane. These two reference layers form an additional high frequency bypass capacitor of approximately 100 pF/in2.
The low speed control signal is routed at the bottom. These signal links have enough headroom to withstand the interruptions caused by vias, resulting in greater flexibility.
The controlled impedance transmission line is a trace of the characteristic impedance Z0 that is always controlled by its geometric characteristics. When the trace length is greater than 15mm (tr=1ns) and 30mm (tr=2ns), the trace impedance must match the isolator output impedance Z0~rO (as shown in Figure 4) to minimize signal reflection. This is called source impedance matching.
Figure 4 Source impedance matching: Z0 ~ rO
The dynamic output impedance r0 of the isolator can be obtained from the linear portion of the approximate voltage-current output characteristic listed in the isolator data sheet. In general, the standard output impedance is approximately 70Ω. Thus, for a standard 2 ounce copper plated wire and a 4.5 FR-4 dielectric, the 8 mm wide, 10 mm long trace geometry on the ground plane will produce the required 70 Ω characteristic impedance.
It is recommended to follow the following main wiring guidelines to maintain signal integrity and low EMI.
In order to reduce the crosstalk to less than 10%, it is necessary to keep the signal trace three times the distance from the high-speed signal layer to the ground plane (d=3h). The return density under the signal trace follows the 1/[1+(d/h)2] function, so its density at d′3h is very low, avoiding large crosstalk in adjacent traces (see Figure 5).
Figure 5 minimizes crosstalk with d = 3h
Use a 45 degree trace bend (or beveled bend) instead of a 90 degree bend to maintain effective trace impedance and avoid signal reflections.
To achieve operation in noisy environments, the idle start input of the isolator is connected to the appropriate reference layer through a resistor (1kΩ to 10kΩ). Connect an active-high, high-bit enable input to the power plane and an active-low input to the ground plane.
When the via inductance increases the signal path inductance, avoid layers changing with fast signal traces.
Using a shorter trace length between the isolator and the surrounding circuitry avoids noise introduction. Digital isolators typically have an isolated DC/DC converter that provides power across the isolation barrier. Since the single-ended transmission signal of the isolator is too sensitive to noise introduction, the switching noise of the adjacent DC/DC converter can be easily introduced by the long signal trace.
Place a large-capacity capacitor (such as 10μF) near a power source such as a voltage regulator, or where the power supply enters the PCB.
Install a small 0.1μF or 0.01μF bypass capacitor on the device by connecting the power supply terminal directly to the power supply terminal of the device and then through the hole to the Vcc layer. Connect the capacitor ground to the ground plane via several vias (see Figure 6).
Figure 6 Connect the bypass capacitor directly to the Vcc terminal
Multiple vias are used to connect bypass capacitors and other protection devices (such as transient voltage suppressors and Zener diodes) to minimize the via inductance of the ground connection.
to sum up
Although there is a lot of information about PCB design, this article mainly provides some suggestions for digital isolator board design. Following these recommendations will help you complete a board design that meets EMC standards in the shortest amount of time.