PCB printed circuit board design high frequency wiring skills
Digital devices are moving in the direction of high speed, low power consumption, small size, and high anti-interference. This trend has put forward many new requirements for the design of printed circuit boards. Based on years of experience in hardware design work, the author summarizes some of the techniques of high-frequency wiring for your reference.
(1) High-frequency circuits tend to have high integration and high wiring density. The use of multi-layer boards is both necessary for wiring and an effective means to reduce interference.
(2) The less the lead bend between the pins of the high-speed circuit device, the better. The lead wire of the high-frequency circuit wiring is preferably a full line, which needs to be turned, and can be folded by a 45° fold line or a circular arc. To meet this requirement, the external transmission and mutual coupling of the high-frequency signal can be reduced.
(3) The shorter the lead between the pins of the high-frequency circuit device, the better.
(4) The less alternating between the wiring layers between the pins of the high-frequency circuit device, the better. The so-called "the minimum number of interlayer crossings is as good as possible" means that the fewer vias (Via) used in the component connection process, the better, it is estimated that one via hole can bring about a distributed capacitance of about 0.5 pF, reducing the number of vias. Can significantly increase the speed.
(5) High-frequency circuit wiring should pay attention to the “cross-interference” introduced by the parallel lines of the signal lines. If parallel distribution cannot be avoided, a large area “ground” can be arranged on the reverse side of the parallel signal lines to greatly reduce interference. Parallel traces in the same layer are almost inevitable, but in the adjacent two layers, the direction of the traces must be taken perpendicular to each other.
(6) A measure of grounding enveloping a particularly important signal line or local unit, that is, drawing the outer contour of the selected object. With this function, the so-called "packet" processing can be automatically performed on the selected important signal lines. Of course, it is also very beneficial for the high-speed system to use this function for the local processing of the components such as the clock.
(7) Various types of signal traces cannot form a loop, and the ground line cannot form a current loop.
(8) A high frequency decoupling capacitor should be placed near each integrated circuit block.
(9) High-frequency turbulence links should be used when connecting analog ground lines and digital ground lines to public ground lines. In the actual assembly of the high-frequency turbulence link, the high-frequency ferrite bead through which the center hole is threaded is often used, and it is generally not expressed on the circuit schematic. The resulting netlist is not Including such components, the wiring will ignore its existence. In response to this reality, it can be used as an inductor in the schematic, and a component package is defined separately in the PCB component library, and it is manually moved to a suitable position near the convergence point of the common ground line before wiring.
(10) The analog circuit and the digital circuit should be arranged separately. After independent wiring, the power supply and ground should be connected at a single point to avoid mutual interference.
(11) Before the DSP, off-chip program memory and data memory are connected to the power supply, the filter capacitor should be added and placed as close as possible to the chip power supply pin to filter out the power supply noise. In addition, shielding is recommended around the DSP and off-chip program memory and data memory to reduce external interference.
(12) The off-chip program memory and data memory should be placed as close as possible to the DSP chip. At the same time, the layout should be reasonable, so that the length of the data line and the address line are basically the same, especially when there are multiple memories in the system, the clock line should be considered to each memory. The clock input distance is equal or a separate programmable clock driver chip can be added. For the DSP system, the external memory with the same access speed as the DSP should be selected, otherwise the high-speed processing capability of the DSP will not be fully utilized. DSP instruction cycle is nanosecond, so the most common problem in DSP hardware system is high frequency interference. Therefore, when making printed circuit board (PCB) of DSP hardware system, special attention should be paid to address lines and data lines. The wiring of the signal line should be correct and reasonable. When wiring, try to make the high-frequency line short and thick, and keep away from the signal lines that are susceptible to interference, such as analog signal lines. When the circuit around the DSP is more complicated, it is recommended to make the DSP and its clock circuit, reset circuit, off-chip program memory, and data memory into a minimum system to reduce interference.
(13) After following the above principles and skillful use of design tools, after manual wiring is completed, high-frequency circuits generally need to use advanced PCB simulation software for simulation in order to improve the reliability and productivity of the system.
Due to space limitations, this article does not give a detailed introduction to the specific simulation, but the suggestion to everyone is that if there are conditions, we must simulate the system, here are a few basic concepts.
Give everyone a basic explanation.
What is electromagnetic interference (EMI) and electromagnetic compatibility (EMC)?
Electromagnetic interference (Electromagnetic InteRFerence) has both conducted and radiated interference. Conducted interference refers to the coupling (interference) of signals on one electrical network to another electrical network through a conductive medium. Radiated interference refers to an interference source that couples (interferes) its signal to another electrical network through space. In high-speed PCB and system design, high-frequency signal lines, integrated circuit pins, various types of connectors, etc. may become radiation interference sources with antenna characteristics, which can emit electromagnetic waves and affect other systems or other subsystems in the system. normal work.
What is signal integrity?
Signal integrity refers to the quality of a signal on a signal line. Signals with good signal integrity are those that have to be reached when needed. Poor signal integrity is not caused by a single factor, but by a combination of factors in the board design. The main signal integrity issues include reflection, oscillation, ground bounce, crosstalk, and so on.
What is reflection (reflecTIon)?
Reflection is the echo on the transmission line. A portion of the signal power (voltage and current) is transmitted to the line and reaches the load, but a portion is reflected. If the source and load have the same impedance, the reflection will not occur. A mismatch between the source and load impedances causes on-line reflections, and the load reflects a portion of the voltage back to the source. If the load impedance is less than the source impedance, the reflected voltage is negative. Conversely, if the load impedance is greater than the source impedance, the reflected voltage is positive. Such reflections can be caused by variations in wiring geometry, incorrect wire termination, transmission through the connector, and discontinuity in the power plane.
What is crosstalk?
Crosstalk is the coupling between two signal lines. The mutual inductance and mutual capacitance between the signal lines cause noise on the line. Capacitive coupling induces a coupling current, while inductive coupling induces a coupling voltage. PCB board layer parameters, signal line spacing, electrical characteristics of the driver and receiver terminals, and line termination methods all have a certain impact on crosstalk.
What is overshoot and undershoot?
Overshoot is the first peak or valley value that exceeds the set voltage—for the rising edge, the highest voltage and for the falling edge, the lowest voltage. Undershoot is the next valley or peak. Excessive overshoot can cause the protection diode to work, leading to premature failure. Excessive undershoot can cause false clock or data errors (misoperations).
What is ringing and rounding?
The phenomenon of oscillation is repeated overshoot and undershoot. The oscillation and surrounding oscillation of the signal are caused by excessive inductance and capacitance on the line. The oscillation belongs to the underdamped state and the surrounding oscillation belongs to the overdamped state. Signal integrity problems typically occur in periodic signals, such as clocks. Oscillation and surround oscillations are caused by a variety of factors, as are reflections. Oscillation can be reduced by proper termination, but it cannot be completely eliminated.
What is the ground plane bounce noise and return noise?
When there is a large current surge in the circuit, it will cause ground plane bounce noise (referred to as ground bounce). If the output of a large number of chips is turned on at the same time, there will be a large transient current flowing through the power plane of the chip and the board. The inductance and resistance of the chip package and the power plane can cause power supply noise, which will cause voltage fluctuations and changes on the true ground plane (0V), which will affect the operation of other components. An increase in the load capacitance, a decrease in the load resistance, an increase in the ground inductance, and an increase in the number of switching devices at the same time may result in an increase in the ground bounce.
Due to the division of the geoelectric plane (including power and ground), for example, the ground layer is divided into digital ground, analog ground, shield ground, etc., when the digital signal goes to the analog ground region, ground plane return noise is generated. The same power layer may be split into 2.5V, 3.3V, 5V, etc. Therefore, in multi-voltage PCB design, the rebound noise and return noise of the geoelectric plane need special attention.
What is the difference between the TIme domain and the frequency domain?
The TIme domain is a process of changing the voltage or current based on time and can be observed with an oscilloscope. It is typically used to find pin-to-pin delays, skews, overshoots, undershoots, and settling TImes.
The frequency domain is a process of changing the voltage or current based on the frequency and can be observed with a spectrum analyzer. It is typically used for comparisons between waveforms and FCC and other EMI control limits.
What is impedance?
The impedance is the ratio of the input voltage to the input current on the transmission line (Z0=V/I). When a source sends a signal to the line, it will block it from driving until 2*TD, the source does not see its change, where TD is the delay of the line.
What is the settling time?
Settling time is the time it takes for an oscillating signal to settle to a specified final value.
What is the pin-to-pin delay?
The pin-to-pin delay is the time between the change of state of the driver end and the change of state of the receiver end. These changes typically occur at 50% of a given voltage. The minimum delay occurs when the output first crosses a given threshold (threshold), and the maximum delay occurs when the output last crosses the voltage threshold (threshold), measuring all of these Happening.
What is skew (skew)?
The offset of the signal is the time offset between the different receivers arriving at the same network. The offset is also used for the time offset achieved by the clock and data on the logic gate.
What is the slope (slew rate)?
The Slew rate is the edge slope (the ratio of the time change associated with the voltage of a signal). The I/O specification (eg PCI) state is between two voltages, which is the slew rate, which is measurable.
What is a quiescent line?
It does not switch during the current clock cycle. Also known as the "stuck-at" line or static line. Crosstalk can cause a static line to switch during a clock cycle.
What is false clocking?
A fake clock means that the clock unconsciously changes state (sometimes between VIL or VIH) across the threshold. Usually caused by excessive undershoot or crosstalk.
What is an IBIS model?
The IBIS (Input/Output Buffer Information Specification) model is a method for quickly and accurately modeling I/O BUFFER based on V/I curve. It is an international standard that reflects the electrical characteristics of chip driving and receiving. It provides a standard. The file format is used to record parameters such as drive source output impedance, rise/fall time, and input load. It is ideal for calculation and simulation of high frequency effects such as oscillation and crosstalk.
IBIS itself is just a file format that shows how to record the different parameters of a chip's driver and receiver in a standard IBIS file, but does not explain how these recorded parameters are used. These parameters need to be used by the IBIS model. Simulation tool to read. To use IBIS for actual simulation, you need to complete the following four tasks.
(1) Obtaining the original source of information about the chip driver and receiver;
(2) Obtain a method for converting original data into an IBIS format;
(3) providing layout and routing information that can be recognized by the computer for simulation;
(4) Provide a software tool that can read IBIS and place and route formats and perform analytical calculations.
IBIS is a simple and intuitive file format that is ideal for circuit simulation tools like Spice (but not Spice, because the IBIS file format cannot be read directly by the Spice tool). It provides a description of the behavior of the drive and receiver, but does not reveal the intellectual property details of the internal construction of the circuit. In other words, vendors can use the IBIS model to illustrate their latest door-level design work without revealing too much product information to their competitors. And, because IBIS is a simple model, when doing a simple load simulation, it can save 10 to 15 times more computation than the corresponding full Spice triode model simulation.
IBIS provides two complete V-I curves representing the drive's high and low states, respectively, as well as a state transition at a determined slew rate. The role of the V-I curve is to provide IBIS with the ability to model nonlinear effects such as protection diodes, TTL totem pole drive sources, and emitter follower outputs.
What is a SPICE model?
SPICE is an abbreviation of Simulation Program with Integrated Circuit Emphasis.
Hardware debugging skills
Some issues that should be noted when debugging hardware. For example, before hardware debugging, the board should be carefully examined to see if there is a short circuit or open circuit (because the PCB layout of the DSP is generally dense and thin, the probability of this happening is relatively high). After power-on, the application feels whether some chips are particularly hot. If you find that some of the chips are hot, you need to immediately power off and recheck the circuit. After troubleshooting, you should check if the crystal is oscillating and the reset is correct and reliable. Then use an oscilloscope to check if the signal of the CLK-OUT1 and CLK-OUT2 pins of the DSP is normal. If it is normal, it indicates that the DSP itself is working normally.
(1) to ensure the stability and reliability of the power supply
Before debugging the DSP hardware system, ensure that the power supply to the test board has good constant voltage and constant current characteristics. In particular, the input voltage of the DSP should be kept at 5.0V ± 0.05V. When the voltage is too low, an error message will appear when writing to the program via the JTAG interface. If the voltage is too high, the DSP chip will be damaged.
(2) Using simulation software to troubleshoot hardware failures
After completing the inspection of the board, the program can be debugged by the simulation software. Since the program code is downloaded to the off-chip program memory in the target system during simulation, it is relatively easy to check for some hardware failures by the simulation software. After power-on, if the simulation software debugging window can't be loaded into the program, there are two possibilities: 1 DSP chip pin has open circuit or short circuit; 2 DSP chip is damaged. If it is the first time to use the simulation software to debug the program, the test board should be powered off at this time, and the soldering of the pins of the DSP chip should be carefully checked. If the software debug window has been properly loaded into the program, it may be that the DSP chip is corrupted. At this time, it is possible to further judge whether the DSP chip is damaged by detecting the impedance of the entire board of the experimental board. If the impedance of the whole board drops sharply, the power supply line for the DSP chip can be cut off to detect the resistance of the DSP chip.
If the software debug window is tunable into the program, but the program being loaded is partially faulty, such as the code for the off-chip program memory or data memory operation becomes .word xxxx, it may be that the off-chip program memory or data memory has failed. Care should be taken to check the memory for shorts or solder joints. If not, further determine if the memory is damaged.