PCB Layout improperly caused the CPU to work unstable solution
In high-speed digital circuits, the power consumption of the CPU tends to increase with the increase of the main frequency. If the PCB layout is improper, it may cause the CPU to work unstable. I have encountered it. When the Marvell 88F6282 CPU is running at 2GHz, the Memory Test is tested. It is found that the CPU often does not work, and the time is not working every time, but this phenomenon does not occur when the CPU is down-converted to 1.6GHz.
Perform the following analysis
Memory Test is a way to verify that the CPU and DDR can work normally under heavy load conditions. When the system is running at 1.6GHz, it is normal, indicating that the CPU and DDR physical connection is OK, when upgrading to 2GHz. There will be no work after this. There are two reasons for this phenomenon: one is timing, especially Set-up Time and Hold TIme is greater than Margin, at 1.6GHz, because the frequency is relatively low, that is, the clock cycle is relative. Speaking longer, so the timing may be able to meet the CPU requirements for accessing DDR, but after upgrading to 2GHz, due to the shortened clock cycle, it is likely that the timing can not meet the requirements, resulting in read and write errors when the CPU accesses the DDR. To verify this idea, we tested the timing of the CPU accessing the DDR at 2 GHz, and the results showed that the timing met the requirements. Another possibility is that the CPU is running low on power, because from the data sheet of the Marvell 88F6282, the CPU consumes 700 mA at 2 GHz when operating at 1.6 GHz.
But when we open our PCB, we find that VCC_CPU provides the current path through the via layer of the third layer of Power layer. It is found that the effective current path width is about 40mil. According to the empirical formula, the 40mil line width can go 1A on the surface. According to the current, this line width cannot meet the CPU power supply requirements.
Top layer VCC_CPU network
Power layer VCC_CPU network
The simpler method is to take a fly from the VCC_CPU power supply to the capacitor at the CPU supply pin. The final method is to change the Layout so that the minimum line width of the VCC_CPU power layer is 80 mils. After the revision, this problem does not occur again.