Chip Industry Series: FinFET Process
When we look at the manufacturing process of mobile phone processors, we often see the concept of "using the XXnm FinFET process". So what does this string of numbers and letters represent?
First, FinFET is an English abbreviation, which is called “Fin Field-Effect Transistor”. The Chinese translation is “Fin Field Effect Transistor”. Of course, “10nm FinFET Process” means “The chip is fabricated by 10nm FinFET” process. Made! After reading it, I looked like a slap in the face.
The full name of the FET is a Field Effect Transistor (FET). First, from MOS, the full name of MOS is Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The structure is shown in the figure. The green area on the left side (silicon) is called the source. The green area on the right (silicon) is called Drain, the middle part of the metal (red) is called the gate, and there is a thin layer of oxide (gray) under the gate because the middle is from the top. The following order is a metal, an oxide, or a semiconductor, and is therefore called a MOS.
How MOSFETs work
The MOSFET works very simply. Inside the transistor, electrons flow from the source to the drain through the channel under the gate (as shown in the figure above). The gate acts as a switch that allows the transistor to effectively control the flow of electrons through on/off commands. If the gate wants to control the on/off instruction set, then the gate oxide layer is required to assist. As a dielectric layer, the gate oxide layer prevents electrons from flowing from the source to the drain when "off" and attracts electrons when "on".
Gate length: the key to semiconductor process improvement
In MOSFETs, the gate length is the smallest and most difficult to fabricate in all configurations, so the gate length is often used to represent the progress of the semiconductor process. This is called the process line width. The gate length will decrease with the advancement of process technology, from the early 0.18 micron, 0.13 micron, to 90 nanometers, 65 nanometers, 45 nanometers, 22 nanometers, to the current state of the art 10 nanometers. The smaller the gate length, the smaller the overall MOSFET, and the smaller the chip that also contains billions of MOSFETs, the smaller the integrated circuit after packaging, and the smaller the handset will be. How small is 10 nanometer? The bacteria are about 1 micron and the virus is about 100 nanometers. In other words, humans' current technology can produce structures with only 1/10 (10 nanometers) of virus.
The shorter the gate length, the faster the chip can run, because the electrons only need to flow a short distance to operate. In addition, shorter distances mean less energy is required for flow, so mobile processors can achieve greater energy efficiency. In simple terms, the smaller the number before the nm unit, the better!
In addition, the thickness of the gate oxide layer also has a large influence on the operating speed. Although a thinner gate oxide can use a lower voltage to make the gate run faster, when it is in the "off" state, it may also increase current leakage because the oxide layer is too thin. Although the amount of current leakage in a single transistor is very small, this is not a small problem, because for mobile processors, it is usually made with billions of transistors! A small problem multiplied by billions has become a big problem!
FinFET was born, bringing semiconductor manufacturing to a new level
The structure of MOSFETs has been in use for more than 40 years since its inception. For chip manufacturers, it is important to continuously upgrade the technology, and strive to make the gate length as small as possible. However, when the gate length approaches 20 nm and below, the closer the source and drain are, the thinner the oxide under the gate, and the gate-to-current control capability drops sharply, causing "current leakage" (Leakage). problem. On the one hand, current leakage will directly increase the power consumption of the chip, bringing additional heat to the transistor; on the other hand, current leakage leads to circuit errors and signal ambiguity. In order to solve the signal blur problem, the chip has to increase the core voltage, increase the power consumption, and fall into an infinite loop.
The smaller the gate length, the smaller the contact area between the gate and the channel, that is, the smaller the influence of the gate on the channel. How can the influence of the gate on the channel (contact area) be maintained?
In order to effectively solve the limitations of the 2D planar structure, the transistor was redesigned into a 3D fin field effect transistor structure. As the name implies, the original 2D structure has a 3D bend, like a fin. In a finned 3D fin field effect transistor structure, the three surfaces of the channel are surrounded by a gate to effectively control current leakage.
Therefore, three professors such as Hu Zhengming, Tsu-Jae King-Liu, and Jeffrey Bokor of the University of California at Berkeley invented the "Fin Field Effect Transistor (FinFET)" to change the original 2D MOSFET. The 3D FinFET, as shown, is called "Fin" because it is constructed like a fin.
Dynamic diagram of planar MOSFET structure to 3D fin field corresponding transistor (FinFET)
The gate length of the FinFET is already less than 25nm, and 7nm of TSMC has also been mass-produced in the second half of 2018. Due to this breakthrough in conductor technology, future chip designers are expected to be able to design supercomputers to be just the size of a nail. FinFETs are derived from an innovative design of the traditional standard transistor, Field-Effect Transistor (FET). In the conventional transistor structure, the gate through which the current is controlled can only control the on and off of the circuit on one side of the gate, which is a planar structure. In the FinFET architecture, the gate is a fish-like fork-like 3D architecture that controls the switching on and off of the circuit on both sides of the circuit. This design can significantly improve circuit control and reduce leakage, as well as significantly reduce the gate length of the transistor.
In addition to the new structural design, the improved controllability allows the gate to use a lower voltage to switch the switch. By lowering the supply voltage, the slope subthreshold swing from the "off" state to the "on" state can be reduced, allowing the fin field effect transistor structure (FinFET) to be turned on using less energy than the planar structure (MOSFET). Closed, which means more energy saving and longer lasting life.
Energy efficiency is not the only advantage of fin field effect transistor technology. In a planar structure, electrons flow from the source to the drain only through one surface under the gate; in a fin field effect transistor structure, electrons can flow between the three surfaces of the fin-shaped 3D structure, increasing the driving force. Or the amount of flowing electrons.
In addition, the shorter gate length of the 10 nm process means faster on/off switching due to the shorter distance of electrons moving from source to drain. If the channel is compared to a road, the number of lanes is increased by several times in a 10 nm fin field effect transistor structure compared to a 20 nm planar structure, and the length of the path that the electrons need to travel is greatly reduced. The lanes widen and the distance becomes shorter, so when more electrons pass through the channel, the performance will undoubtedly increase dramatically.
Therefore, the current FinFET process enables the highest levels of efficiency and performance.