Western Digital SweRVs Towards Open Source with New RISC-V Core, ISS, and Cache Coherency
Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's open-source ISA (instruction set architecture) a year ago. This month, they announced a series of open-source, collaborative initiatives that aim to make data more open, from processor cores to memory caches.
At the inaugural RISC-V summit this December, there were many announcements and presentations detailing the state of RISC-V and its impact—present and future—on the industry.
Western Digital, a company best known for data storage devices, is one of the companies in the growing RISC-V environment. One year ago, they announced that they were moving to RISC-V. Now, they're doubling down on their commitment to this open source architecture, aiming to facilitate new innovation and help lead the charge into the future of data processing and, eventually, data storage.
At the summit, Western Digital announced three pieces of news, each related to their efforts in working in the open source space:
- OmniXtend: a memory fabric
- SweRV Core: a RISC-V core developed in-house
- SweRV ISS: an instruction set simulator
AAC had the chance to speak to Ted Marena, Director of RISC-V Ecosystem at Western Digital, about these new developments and how the company is approaching the open source phenomenon.
Big Data vs. Fast Data, Core Computing vs. Edge Computing
Marena and Western Digital overall characterize the differences between big data in several ways.
Big data is often processed in a core location with its own processing and tends to face issues such as scalability. Fast data, on the other hand, is more relevant to edge computing where fast responses are important, making performance and latency among the chief challenges.
An example of an edge computing application, where latency is a pain point, is a security camera. The system doesn't have time to send information to the cloud where decisions can be made based on the data—it needs a smaller, more simple solution.
And the market is likely to see an increasing trend towards edge applications, which will require more processing and intelligence.
Why Open Source Is the Future
According to Marena, a big reason that Western Digital made a distinct leap into partnering with the RISC-V organization was that they were finding that general-purpose architectures were difficult to work with due to their proprietary interfaces. Going back as far as 2014, the company had begun to believe that open, standard interfaces were pivotal to innovation.
Another piece of this puzzle is that ever-present bogeyman, security. The overall trend, Marena says, is that open source is more secure due to "more eyes" on the situation in a collaborative situation.
Opting into Open Standards
There are other standards developed by consortiums in this space, says Marena, (some of which Western Digital is involved in) and some of them are not open source. Convincing an industry to adopt an open standard is a challenge in and of itself. Such a standard wouldn't be possible for most existing architectures. When asked about how Western Digital is trying to promote open standards, Marena explained the company's booth demo at the RISC-V Summit. Partnering with SiFive for a point-to-point solution and Barefoot Networks for a programmable switch, Western Digital showcased their new memory fabric, OmniXtend.
This is a case of "proving by doing" where Western Digital hopes to build support for an open standard by showing that it's useful and effective.
Here's an overview of what these collaborations—and Western Digital's focus on RISC-V—have wrought.
OmniXtend: Cache Coherence for Big Data and Fast Data
OmniXtend is a cache-coherent "memory fabric" designed to allow shared access to a memory cache between multiple different types of processors. The idea is that multiple parties (people or processors, etc.) will have access to the same memory, allowing better coherency across a system.
"Basically, we're proposing this memory fabric which would allow, say, a RISC-V processor, a GPU, and an FPGA to all share and have access to the cache in a coherent manner. This doesn't have to be just a RISC-V implementation. You could have other processor architectures that could adopt this standard. The shift here," Marena says, "is that, in today's architectures, the ratio of memory-to-processor or memory-to-peripherals is fairly fixed and set. What we're looking to do is make data more the center of the architecture. Nobody owns the memory and therefore we think that this can introduce some really unique solutions."
"What we're looking to do is make data more the center of the architecture."
Marena frames cache coherency in terms of processing-hungry applications. Artificial intelligence, for example, requires a great deal of processing. In this scenario, a large number of AI processors could share memory across a network. Western Digital thinks that this would allow specific applications to be implemented in the near future that today could require a different ratio than what's currently supported.
"RISC-V allows us to do this because it's open," Marena added. "This kind of standard would not be possible with some of the existing architectures."
SweRV Core: A RISC-V Core
SweRV Core is the first RISC-V-designed core, which will be released as completely open source in the first few months of 2019. It was developed by Western Digital to be used in-house but then released as a contribution to the open source ecosystem.
Marena first broke down the thinking behind the name "SweRV": RV is for RISC-V and "we" is a nod to both the collaborative nature of the project and the Western Digital name. SweRV is also the verb for taking another path, he says, highlighting the company's commitment to facilitating change in the industry.
"And that's really what we're doing," he says. "We're not utilizing general-purpose compute. We want to utilize RISC-V to allow us to come up with purpose-built architectures for big data and fast data."
The core, itself, is an in-order core, meaning that it executes instructions one at a time.
Marena says this kind of core is a simpler design that allows it to be smaller and less power-hungry. He also suggests that in-order cores are less susceptible to certain security attacks.
The concept is that the core can serve as a jumping-off point for developers to create their own custom cores, especially the open-source community. To facilitate the capability for designers to adopt and build on the core, they also intend to provide test vectors. As Marena puts it, "We're excited to see what people can do."
SweRV ISS (Instruction Set Simulator)
Finally, Western Digital announced their ISS, which allows users to emulate and simulate what a processor is doing, essentially making sure that a design is doing what it's supposed to do.
Marena says that the "key bullet point" for the ISS is that it's implemented independently from the SweRV core RTL. The core's Verilog RTL was developed by a completely separate team from the one working on the SweRV ISS. They were instructed to develop an ISS that would respond to RISC-V instructions, even if the core being used was external (i.e., not from Western Digital)—something able to test anything they put through the software.
"This gives people a production-ready core they can build upon," says Marena.
The Future: RISC-V Storage Devices
While it may seem mildly odd to see a data storage device company putting forth cores and simulators, there is a larger plan at work. In late 2019 or possibly 2020, says Marena, Western Digital plans to release RISC-V data storage devices.
"It's all about open standard interfaces," he says.
What's your familiarity with RISC-V? What do you think of these new trends towards open source architectures? Share your thoughts in the comments below.