Intel's new Agilex FPGAs create a data-centric world
Intel today announced a new family of products, Intel® AgilexTM FPGAs. The new Field Programmable Gate Array (FPGA) family will provide tailored solutions to address the unique data-centric business challenges of the embedded, network and data center markets.
Dan McNamara, senior vice president of Intel Programmable Solutions, said: "Fast resolution of data-centric issues requires an agile, flexible solution to efficiently transfer, store and process data. Intel Agilex FPGAs not only provide custom connectivity And acceleration, and can significantly improve performance and reduce power consumption for a variety of workloads1,2."
Customers need superior solutions to help consolidate and process the ever-increasing volume of data traffic, enabling emerging data-driven industries such as edge computing, networking, and cloud to run a variety of transformative applications. Whether it's edge analysis for low-latency processing, virtualized networking for performance, or data center acceleration for efficiency, Intel Agilex FPGAs offer custom solutions for everything from edge to cloud. In the areas of edge, network, and cloud computing, advances in artificial intelligence (AI) analysis can help hardware systems adapt to changing standards, support a variety of AI workloads, and integrate multiple functions. Intel Agilex FPGAs provide the flexibility and agility needed to help solve these challenges while improving performance and reducing power consumption1,2.
The Intel Agilex family seamlessly combines FPGA fabrics built on Intel's 10nm process technology with innovative heterogeneous 3D SiP technology to integrate analog, memory, custom computing, custom I/O, Intel eASIC and FPGA logic structures into one In the chip package. With a custom logic continuum with reusable IP, Intel can provide a migration path from the FPGA to the structured ASIC. An API provides a software-friendly heterogeneous programming environment that allows software developers to easily take advantage of FPGAs to accelerate.
Intel Agilex FPGAs offer several new features to help accelerate future-proof solutions. These innovations are as follows:
1.Compute Express Link: The industry's first FPGA to support Compute Express Link, a cache and memory-consistent interconnect structure for future Intel® Xeon® scalable processors.
2. Second-generation HyperFlex architecture: Up to 40% performance improvement or 40% reduction in total power consumption 2 compared to Intel® Stratix® 10 FPGAs. 1
3. DSP Innovation: The only FPGA that supports hardcore BFLOAT16 and up to 40 teraflops (FP16) digital signal processing (DSP) performance. 3
4. Fifth Generation Peripheral Component Interconnect Bus (PCIe): Higher bandwidth than PCIe Gen 4.
5. Transceiver Data Rate: Supports data rates up to 112 Gbps.
6. Advanced memory support: DDR5, HBM, Intel® AoTengTM DC permanent memory support.
More details on Intel Agilex performance, power, and software support data:
1 Up to 40% performance improvement over Intel StraTIx 10 FPGAs
The data was derived from the benchmark of the sample design kit, which compares the maximum clock speed (Fmax) achieved by Intel StraTIx 10 devices and Intel Agilex devices using Intel Quartus Prime software, respectively. Based on the February 2019 test, on average, designs running at the fastest speed grades of Intel Agilex FPGAs have improved Fmax compared to designs running at the most common speed grades (-2 speed grades) of StraTIx 10 devices. 40%.
2 Total power consumption reduced by up to 40% compared to Intel StraTIx 10 FPGAs
The data is derived from benchmarking the sample design suite, comparing the estimated total power consumption of designs running in Intel Stratix 10 FPGAs with the total power consumption of designs running in Intel Agilex FPGAs. The test was conducted in February 2019, and the power estimates for the Intel Stratix 10 FPGA design were based on the Intel Stratix 10 Early Power Estimator; the power estimates for the Intel Agilex FPGA design were based on Intel internal analysis and architecture simulation and modeling. Out.
3 up to 40 TFLOP DSP performance (FP16 configuration)
Each Intel Agilex DSP module performs FP16 floating point operations (FLOP) twice per clock cycle. The total FLOP in the FP16 configuration is obtained by multiplying the maximum number of DSP blocks available in a single Intel Agilex FPGA by the maximum clock frequency specified by the module.